
#include 	"main.h"

/********************************************************
**函数名：SystemCoreClockConfigure
**功能：	配置系统内核时钟
**输入：	无
**返回值：无
**注意：	
********CLK Source***************************************
**      0001b System OSC (SOSC_CLK)
**      0010b Slow IRC (SIRC_CLK)
**      0011b Fast IRC (FIRC_CLK)
**      0110 System PLL (SPLL_CLK)
********计算公式***************************************
*       1.VCO_CLK=SPLL_SOURCE / (PREDIV + 1) x (MULT + 16)
*       2.SPLL_CLK=(VCO_CLK) / 2
*       3.SYS_CLK=SPLL_CLK / DIVCORE
*       4.BUS_CLK=SYS_CLK / DIVBUS
*       5.FLASH_CLK=SYS_CLK / DIVSLOW
*********************************************************
**      System Clock source 	PLL (OSC)
**      外部晶振f_osc               8MHz
**      OSC Frequency(Hz)		8000000
**      SYSCLK(Hz)				8000000
**      PLLMUL                  40(24+16)
**      PREDIV                  1(0+1)
**      SPLLCLK(MHz)            160MHz[(8MHz / (0+1) * 40) / 2]
**      SYSCLK/CORECLK(MHz)     80MHz
**      BUSCLK(MHz)             40MHz
**      FLASH_CLK(MHz)          26.67MHz
*********************************************************/
void BSW_SYS_CONFIG(void) 
{
    //SOSC=8MHz
    SCG_ClearSoscControl(SCG);                                  /*Clears SOSC control register*/
    SCG_SetSoscAsyncConfig(SCG,1,1);                            /*SOSC_CLKDV1 = 1*/
                                                                /*SOSC_CLKDV2 = 1*/
    SCG_SetSoscConfiguration(SCG,2,0,1);                        /*系统0SC范围选择中等频率 低增益模式 选择SOC晶体振动器*/
                                                                /*Range=2: 选择晶体振荡器的中频范围 (SOSC 1MHz-8MHz)*/
                                                                /*gain:HGO=0:   控制晶体振荡器的工作功率模式 --低功率模式*/
                                                                /*extRef:EREFS=1: 外部参考选择OSC内部晶体振荡器*/
    SCG_SetSoscControl(SCG,false,false,false);                  /* Enable clock. */
                                                                /* LK=0:          SOSCCSR can be written */
                                                                /* SOSCCMRE=0:    OSC CLK monitor IRQ if enabled */
                                                                /* SOSCCM=0:      OSC CLK monitor disabled */
                                                                /* SOSCERCLKEN=0: Sys OSC 3V ERCLK output clk disabled */
                                                                /* SOSCLPEN=0:    Sys OSC disabled in VLP modes */
                                                                /* SOSCSTEN=0:    Sys OSC disabled in Stop modes */
                                                                /* SOSCEN=1:      Enable oscillator */
    while (!SCG_GetSoscStatus(SCG)) ;                           /* Wait for OSC clock to be valid. */

    //SIRC  8MHz--source:2
    SCG_ClearSircControl(SCG);                                  /* Init SIRC */
    SCG_SetSircAsyncConfig(SCG,1,2);                            /* SIRC_CLKDV1 = 1*/
                                                                /* SIRC_CLKDV2 = 2*/
    SCG_SetSircConfiguration(SCG,1);                            /* Set SIRC的频率范围8M*/
    SCG_SetSircControl(SCG,false,false,false);                  /* Enable clock	*/
    while (!SCG_GetSircStatus(SCG));                            /* Wait for SIRC clock to be valid. */
    SCG_SetRunClockControl(SCG,2,0,0,3);                        /* 选择SIRC作为system clock source 分频为4 */
    while (SCG_GetRunSystemClockSource(SCG)!= 0x02) ;           /* Wait for clock source switch finished. */

    //FIRC 48MHz--source:3
    SCG_ClearFircLock(SCG);                                     /* Init Firc */
    SCG_SetFircAsyncConfig(SCG,1,1);                            /* FIRC_CLKDV1 = 1 */
                                                                /* FIRC_CLKDV2 = 1 */
    SCG_SetFircConfiguration(SCG,0);                            /* Set FIRC configuration. */
    SCG_SetFircControl(SCG,false,false);                        /* Enable clock. */
    while (!SCG_GetFircStatus(SCG));                            /* Wait for FIRC clock to be valid. */

    //SPLL Init 160MHz--source:6
    SCG_ClearSpllControl(SCG);                                  /* Init SysPll */
    SCG_SetSpllAsyncConfig(SCG,SCG_ASYNC_CLOCK_DIV_BY_2,SCG_ASYNC_CLOCK_DIV_BY_4);  
                                                                /* SPLL_CLKDV1 = 2 */
                                                                /* SPLL_CLKDV2 = 4*/
    SCG_SetSpllConfiguration(SCG,SCG_SPLL_CLOCK_PREDIV_BY_1,SCG_SPLL_CLOCK_MULTIPLY_BY_40); /* Set PLL configuration. */
                                                                /* PREDIV=0: Divide SOSC_CLK by 0+1=1 */
                                                                /* MULT=24:  Multiply sys pll by 16+24=40 */
                                                                /* VCO_CLK = SPLL_SOURCE/(PREDIV+1)*(MULT+16) */
                                                                /* SPLL_CLK = (VCO_CLK)/2 */
                                                                /* SPLL_CLK = (8MHz / (0+1) * 40) / 2 = 160 MHz */
    SCG_SetSpllControl(SCG,false,false,false);					/* Enable clock. */
                                                                /* LK=0:        SPLLCSR can be written */
                                                                /* SPLLCMRE=0:  SPLL CLK monitor IRQ if enabled */
                                                                /* SPLLCM=0:    SPLL CLK monitor disabled */
                                                                /* SPLLSTEN=0:  SPLL disabled in Stop modes */
                                                                /* SPLLEN=1:    Enable SPLL */
    while (!SCG_GetSpllStatus(SCG));                            /* Wait for SPLL clock to be valid. */
    SCG_SetRunClockControl(SCG,6,1,1,2);                        /* 选择SPLL作为system clock source */
                                                                /* PLL as clock source*/
                                                                /* DIVCORE=1, div. by 2: Core clock = 160/2 MHz = 80 MHz*/
                                                                /* DIVBUS=1, div. by 2: bus clock = 40 MHz*/
                                                                /* DIVSLOW=2, div. by 3: SCG slow, flash clock= 80/3=26.67 MHz*/
    while (SCG_GetRunSystemClockSource(SCG)!= 0x06);            /* Wait for clock source switch finished. */

}


void BSW_SYS_SoftReset(void)
{
    void	(*pf_soft_reset)(void);
    pf_soft_reset = 0;
    pf_soft_reset();
}































